Thin films of dielectric materials find a number of applications in today's IC fabrication technology including primary passivation and diffusion masking, interlevel dielectric insulation, overcoat passivation, and etch-masking. In all cases except one, the primary passivation and diffusion masking of silicon wafers where thermally grown oxide of silicon (SiO.sub.2) is utilized, the dielectric films have conventionally been produced by the chemical vapor deposition (CVD) of inorganic glasses such as undoped and doped silica (SiO.sub.2) silicon nitride (Si.sub.3 N.sub.4).
The use of CVD processes to deposit dielectric films is associated with several problems including difficult control of film uniformity and composition, high level of pinhole and particulate type defects, handling of toxic and hazardous gases (e.g., silane, SiH.sub.4 and phosphine, PH.sub.3), and poor step-coverage (lack of planarization). The densely packed LSI (Large Scale Integration) and VLSI (Very Large Scale Integration) circuits are fabricated by utilizing multiple levels of conducting interconnect patterns separated by insulating layers.
The lack of ability in CVD films to planarize the underlying substrate topography is a particularly serious problem when CVD films are employed as an interlevel dielectric insulation layer that results in greatly reduced manufacturing yields and reliability of finished ICs.
Several techniques for effecting a partial planarization or smoothing of the CVD SiO.sub.2 films have been developed over the years. In the so-called "Reflow Glass" processes, a CVD SiO.sub.2 film containing 6-8% P is deposited on a substrate with first level interconnect and the substrate is subsequently heated in a diffusion furnace to a temperature of about 1050.degree. C. for 15-30 minutes. Because of the high amounts of phosphorus, the softening point of the phosphosilicate glass is low enough that a partial flow of the film occurs resulting in a smoothing of the substrate topography. The process requires that the first level metallization material be resistant to the effect of thermal treatment at the reflow temperatures. Except in the case of the first level interconnect in MOS (Metal-Oxide-Semiconductor) device fabrication where polysilicon metallization is utilized, the interconnect generally consists of aluminum or aluminum alloys which cannot be subjected to temperatures much above 500.degree. C. Thus, the Reflow Glass process is not universally applicable in interlevel insulation processes. Furthermore, in the State-of-the-Art technology the high temperature treatment produces two undesirable effects: dopant redistribution (change in dopant profiles) and substrate damage due to thermal stress. Other techniques for the planarization of deposited (CVD) film topography are based on external physical processes such as energetic ion-induced etching. However, such processes tend to be slow (low throughput), equipment-intensive, and liable to cause radiation damage in the substrate.
An alternative method to chemical vapor deposition is the application of thin dielectric films to substrates by the spin-on technique. In the spin-on process, a solution of an appropriate polymeric material is dispensed onto a substrate and the substrate rotated at high speeds (1-10,000 rpm) for a period of 10 seconds or so whereby a highly uniform film of the polymeric material is formed on the substrate. Following the spin-on application the film is dried and cured as necessary. Spun-on films have the inherent quality of planarizing the underlying substrate topography. Therefore, the spin-on processes offer a particularly desirable method of depositing dielectric layers for interlevel insulation and, in general, other applications in IC fabrication technology. However, the spin-on material/film, in order to be useful must meet a set of stringent requirements including: high mechanical integrity and quality, low density of microdefects (pinholes and particulates), good adhesion characteristics, suitable dielectric properties, resistance to chemical attack, low cure temperature, thermal stability, and compatibility with other materials and further IC fabrication processes. The film thickness range generally required is 1-3 microns.
In prior practice, polyimides, a class of high temperature organic polymers, have been evaluated as a spin-on dielectric material for a number of years. Although polyimides have adequate dielectric characteristics and can be spin-applied into films several microns thick, their use in IC fabrication technology has not been widespread. This is because of the difficult cure and processing involved with the use of polyimide films as well as certain inherent material limitations, including high moisture content of polyimide films, poor adhesion to substrate, and the degradation of dielectric properties at elevated temperatures. Thus, even though polyimides have been investigated as spin-on dielectric film materials, due to difficult processing requirements and some inherent shortcomings in material characteristics, they have not gained widespread use. Accordingly a need exists for improved film forming composition/systems for use in connection with integrated circuit manufacture.